2026-09-19T07:25:29Zhttps://api.mountainscholar.org/server/oai/request

oai:mountainscholar.org:10217/810542025-12-30T03:19:14Zcom_10217_100532com_10217_100000com_10217_100411com_10217_100303col_10217_100538col_10217_100415

Pimpalkhute, Tejasi, author Pasricha, Sudeep, advisor Bohm, Wim, committee member Jayasumana, Anura, committee member 2007-01-03T06:11:33Z 2015-01-31T05:57:00Z 2013 Pimpalkhute_colostate_0053N_12147.pdf ETDF2013500410ECEN http://hdl.handle.net/10217/81054 https://doi.org/10.25675/3.018453 In chip multi-processor (CMP) systems, communication and memory access both play an important role in influencing the performance achievable by the system. The manner in which the network packets (on-chip cache requests/responses) and off-chip memory bound packets are handled, in multi-core environment with several applications executing in parallel, determines end-to-end latencies across the network and memory. Several techniques have been proposed in the past that schedule packets in either an application-aware manner or memory requests in a DRAM row/bank locality-aware manner. Prioritization of memory requests is a major factor in increasing the overall system throughput. Moreover, with the increasing diversity in CMP systems, applying the same prioritization rules to all packets traversing the NoC as is done in the current implementations may no longer be a viable approach. In this thesis, a holistic framework is proposed that integrates novel prioritization techniques for both network and memory accesses and operates cohesively in an application-aware and memory-aware manner to optimize overall system performance. The application-aware technique makes fine grain classification of applications with a newly proposed ranking scheme. Two novel memory-prioritization algorithms are also proposed, one of which is specifically tuned for high-speed memories. Upon analyzing the fairness issues that arise in a multi-core environment, a novel strategy is proposed and employed system-wide to ensure fairness in the system. The proposed heterogeneous prioritization framework is validated using a detailed cycle-accurate full system event-driven simulator and shows significant improvement over Round Robin and other recently proposed network and memory prioritization techniques. born digital masters theses English eng Colorado State University. Libraries 2000-2019 Copyright and other restrictions may apply. User is responsible for compliance with all applicable laws. For information about copyright law, please see https://libguides.colostate.edu/copyright. multi-core systems off-chip memory network-on-chip Heterogeneous prioritization for network-on-chip based multi-core systems Text 2015-01-31 2015-01-31 This Item is protected by copyright and/or related rights (https://rightsstatements.org/vocab/InC/1.0/). You are free to use this Item in any way that is permitted by the copyright and related rights legislation that applies to your use. For other uses you need to obtain permission from the rights-holder(s). Master of Science (M.S.) Masters Electrical and Computer Engineering Colorado State University open.access